There is a need in the integrated circuit art for obtaining increasingly smaller devices without sacrificing device performance. The small device size requires small device regions, precise and accurate alignment between regions, and minimization of parasitic resistances and capacitances. Device size can be reduced by putting more reliance on fine line lithography, but as discussed below, it becomes impractical or impossible to continue to reduce feature size and achieve the required greater increase in alignment accuracy. As lithography is pushed to its physical limits, yield and production throughput decrease.
Four governing performance parameters of a photolithographic system are limit-of-resolution, Lr, level-to-level alignment accuracy, depth-of-focus, and throughput. For purposes of this discussion, limit-of-resolution, level-to-level alignment, and depth-of-focus are physically constrained parameters.
Typical photolithographic techniques are limited by physical constraints of the photolithographic system involving actinic radiation wavelength, λ, and geometrical configurations of the projection system optics. According to Rayleigh's criterion,
      L    r    =            0.61      ⁢      λ        NA  where NA is the numerical aperture of the optical system and is defined as NA=n sin α, where n is the index of refraction of the medium which the radiation traverses (usually air for this application, so n≅1) and α is a half-angle of the divergence of the actinic radiation. For example, using deep ultraviolet illumination (DUV) with λ=193 nm, and NA=0.7, the lower limit of resolution is 168 nanometers (1680 Å). Techniques such as phase shifted masks can extend this limit downward, but photomasks required in this technique are extremely expensive. This expense becomes greatly compounded with a realization that an advanced semiconductor process may employ more than 25 photomasks.
Along with the limit-of-resolution, the second parameter, level-to-level alignment accuracy becomes more critical as feature sizes on photomasks decrease and a number of total photomasks increases. For example, if photomask alignment by itself causes a reduction in device yield to 95% per layer, then 25 layers of photomask translates to a total device yield of 0.9525=0.28 or 28% yield (assuming independent errors). Therefore, a more complicated mask, such a phase shifted mask is not only more expensive but can cause device yield to suffer dramatically.
Further, although the numerical aperture of the photolithographic system may be increased to lower the limit-of-resolution, the third parameter, depth-of-focus, will suffer as a result. Depth-of-focus is inversely proportional to NA2. Therefore, as NA increases, limit-of-resolution decreases but depth-of-focus decreases more rapidly. The reduced depth-of-focus makes accurate focusing more difficult especially on non-planar features such as “Manhattan Geometries” becoming increasingly popular in advanced semiconductor devices.
Recently, techniques have been developed to make smaller scale transistors and related devices. One such method of making transistors is described in a paper presented at the 1999 International Electron Devices Meeting and sponsored by IEEE, entitled “The Vertical Replacement-Gate (VRG) MOSFET: A 50-nm Vertical MOSFET with Lithography-Independent Gate Length, by J. M. Hergenrother et al. Here, Hergenrother et al. describes a method utilizing a vertical transistor technology wherein the gate and gate oxide are required to be applied in the final steps of the process.
U.S. Pat. No. 6,413,802 to Hu et al., describes a device fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin.
Further, U.S. Pat. No. 6,525,403, to Inaba et al., describes a process with a gate, source, and drain in a modified horizontal configuration.
U.S. patent application Publication No. 2002/0060338 by Zhibo Zhang describes a vertical FET device whereby source and drain regions are formed at respective ends of a vertical channel, and an insulated gate is formed adjacent the vertical channel.
Still other art has focused on vertical devices like those mentioned above with formation occurring on silicon-on-insulator (SOI). SOI and SIMOX have several disadvantages. These disadvantages include poor performance for memory devices (since the body of the device is floating), a requirement for extreme lithography on one or more of the process steps, and a drastic increase in price for the SOI material.
Additionally, in a conventional method for fabricating a bipolar device, a source window is directly opened without some means of providing an etch stop. A potential overetch produces a damaged region in the silicon and may result in excessive consumption of silicon underlying a contact. Further, formation of an oxide spacer without an etch stop presents manufacturing difficulties as timing and other recipe tolerances become overly stringent.
For at least the aforementioned reasons, integrated circuit manufacturers have been unable to sufficiently reduce a size of electronic devices while still maintaining high performance. The aforementioned art has limitations on either device performance or manufacturability due to structures used (e.g., SOI or SIMOX), limitations due to required lithography steps, or requirements for gate oxides to be performed late in a process, thereby limiting flexibility in design. In view of the desire for integrated circuits having higher device counts, smaller device sizes, and greater circuit performance, a need continues to exist for an improved process to manufacture the required devices without resorting to unrealistic and expensive photolithography requirements.
Accordingly, what is needed is a way to provide an improved process and structure for fabricating integrated circuit devices. Such a structure for producing integrated circuit devices would have devices with a reduced size with reasonable photolithographic tolerances.